1. Field of the Invention
This invention relates to a solid-state image pickup device represented by a CMOS image sensor and a camera system.
2. Description of the Related Art
In recent years, attention is paid to a CMOS image sensor as a solid-state image pickup device or image sensor in place of a CCD image sensor.
This is because the CMOS image sensor overcomes various problems such as a problem that, since a plurality of power supply voltages are required for operation and a plurality of peripheral ICs must operate in combination, the system is much complicated.
The CMOS image sensor has such a plurality of significant merits as described below. In particular, the CMOS image sensor can be fabricated using a fabrication process similar to that for fabrication of popular CMOS type integrated circuits and can be driven with a single power supply. Further, the CMOS image sensor allows mixed formation of analog circuits and logic circuits in the same chip using a CMOS process, and therefore, the number of peripheral ICs can be reduced.
An output circuit of a CCD image sensor in most cases outputs a 1-channel (ch) output using a floating diffusion (FD) amplifier having an FD layer.
In contrast, a CMOS image sensor includes an FD amplifier for each pixel and in most cases outputs such parallel column outputs by selecting a certain row of a pixel array and reading out the pixels in the row at the same time in a direction along the columns.
This is because it is difficult for the FD amplifiers disposed in the pixels to have a sufficient driving capacity and, accordingly it, is necessary to use a low data rate. It is advantageous to use parallel processing.
In the following, a popular CMOS image sensor is described.
FIG. 1 shows an example of a pixel of a CMOS image sensor formed from four transistors.
Referring to FIG. 1, the pixel 1 includes, for example, a photodiode 11 as a photoelectric conversion device. The pixel 1 further includes four transistors including a transfer transistor 12, an amplification transistor 13, a selection transistor 14 and a reset transistor 15 as active devices for the photodiode 11.
The photodiode 11 photoelectrically converts incoming light into charge, here, electrons, whose amount corresponds to the light amount of the incoming light.
The transfer transistor 12 is connected to the photodiode 11 and a floating diffusion FD and transfers electrons produced by photoelectric conversion by the photodiode 11 to the floating diffusion FD when a driving signal is applied to the gate, that is, a transfer gate, thereof through a transfer control line LTx.
The amplification transistor 13 is connected at the gate thereof to the floating diffusion FD. The amplification transistor 13 is connected to a signal line LSGN through the selection transistor 14 and cooperates with a constant current source outside the pixel to form a source follower.
An address signal is applied to the gate of the selection transistor 14 through a selection control line LSEL, and if the selection transistor 14 is turned on, then the amplification transistor 13 amplifies the potential at the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line LSGN. A voltage outputted from each pixel is outputted to a pixel output data parallel-serial processing section through the signal line LSGN.
The reset transistor 15 is connected between a power supply line LVDD and the floating diffusion FD and resets the potential at the floating diffusion FD to the potential of the power supply line LVDD when a reset signal is applied to the gate of the reset transistor 15 through a reset control line LRST.
FIG. 2 shows an example of a general configuration of a CMOS image sensor or solid-state image pickup device wherein such pixels as shown in FIG. 1 are arrayed in a two-dimensional array.
Referring to FIG. 2, the CMOS image sensor 20 shown includes a pixel array section 21, an address decoder 22, a pixel driving pulse generation circuit 23, and a level shifter group 24. The CMOS image sensor 20 further includes a pixel output data parallel-serial processing section 25, an output circuit section 26, a sensor control section 27, and external power supplies 28 and 29 each in the form of a cell.
In the CMOS image sensor 20, a power supply voltage VDD is supplied to the address decoder 22, pixel driving pulse generation circuit 23, pixel output data parallel-serial processing section 25, output circuit section 26 and sensor control section 27 in the inside of a chip from the power supply 28. Meanwhile, another power supply voltage VDD is supplied to the level shifter group 24 and the pixel array section 21 from the power supply 29.
In the CMOS image sensor 20, the sensor control section 27 generates an address for designating a pixel array row to be accessed and sends the address to the address decoder 22.
The address decoder 22 renders an output thereof corresponding to the designated pixel row active. Then, to the row designated by the address decoder 22, a pixel reset pulse LRST and pixel readout pulses LTx and LSEL are supplied to the pixels 1 for each row from the pixel driving pulse generation circuit 23. Image outputs from the pixels 1 are transferred for each row through the signal line LSGN to the pixel output data parallel-serial processing section 25.
Then, image data are outputted for one by one pixel from the pixel output data parallel-serial processing section 25, and the output data are outputted to the outside of the chip through the output circuit section 26.
The sensor control section 27 is a control logic circuit which controls the series of operations.
Referring to FIG. 1 again, in order to reset the pixel, the transfer transistor 12 is turned on to sweep out charge accumulated in the photodiode 11. Thereafter, the transfer transistor 12 is turned off, and the photodiode 11 converts a light signal into charge and accumulates the charge.
Upon reading out, the reset transistor 15 is turned on to reset the floating diffusion FD, and then the reset transistor 15 is turned off and the voltage at the floating diffusion FD then is outputted through the amplification transistor 13 and the selection transistor 14. The output in this instance is hereinafter referred to as P-phase output.
Thereafter, the transfer transistor 12 is turned on to transfer the charge accumulated in the photodiode 11 to the floating diffusion FD, and the voltage at the floating diffusion FD at this time is outputted through the amplification transistor 13. The output in this instance is hereinafter referred to as D-phase output.
By setting the difference between the D-phase output and the P-phase output to an image signal, not only a dispersion of the DC component of the output of each pixel but also FD reset noise of the floating diffusion can be removed from the image signal.
The operations described are carried out simultaneously for pixels of one row since, for example, the gates of the transfer transistors 12, selection transistors 14 and reset transistors 15 are connected in a unit of a row.